Building CMOS Logic Gates: NAND and NOR

Hello! In our previous lesson, we established a clear picture of how individual N-channel and P-channel MOSFETs function as efficient, voltage-controlled switches. We saw that an N-channel MOSFET is excellent at creating a path to ground (a "pull-down" switch), while a P-channel MOSFET excels at creating a path to the positive voltage supply (a "pull-up" switch).

This lesson marks a significant step in your journey to see "how every dot connects." We will now combine these complementary transistors to build the workhorses of the digital world: CMOS NAND and NOR gates. You'll learn how their clever pairing not only implements logic but also gives CMOS technology its signature low-power advantage. By the end of this lesson, you will be able to trace the operation of these fundamental gates at the transistor level, moving from a single switch to a true computational element.

The "Complementary" in CMOS Logic

The name CMOS stands for Complementary Metal-Oxide-Semiconductor. The "complementary" part is key. Instead of using just one type of transistor, CMOS logic pairs an N-channel MOSFET with a P-channel MOSFET. This pairing is designed to solve major problems found in older logic families, such as high power consumption.

Let's start with the simplest possible logic gate: an inverter, or a NOT gate.

The operation is beautifully simple and efficient:

• When Input is LOW (0V):

  • The N-MOSFET is OFF (since $V_{GS}<V_{th}$). The path to ground is broken.
  • The P-MOSFET is ON (since its gate is low relative to its source at $V_{DD}$). The path to $V_{DD}$ is complete.
  • The output is pulled HIGH.

• When Input is HIGH ($V_{DD}$):

  • The N-MOSFET is ON (since $V_{GS}>V_{th}$). The path to ground is complete.
  • The P-MOSFET is OFF (since its gate is high, at the same potential as its source). The path to $V_{DD}$ is broken.
  • The output is pulled LOW.

The following video provides an excellent animated walkthrough of this exact process.

The critical insight here is that in either stable state (output high or low), one of the transistors is always off. This means there is never a direct path from $V_{DD}$ to ground. This lack of a static current path is what makes CMOS logic incredibly power-efficient, allowing for the integration of billions of gates onto a single chip.

The video below elaborates on this advantage, contrasting the CMOS approach with less efficient designs that use only one type of transistor.

Building NAND and NOR Gates

Now that we understand the pull-up/pull-down principle, we can extend it to create multi-input gates like NAND and NOR. The design follows a fascinating rule of duality.

• The pull-down network (PDN), built with N-MOSFETs, implements the gate's primary logic. For example, to get a low output for an AND condition, we connect N-MOSFETs in series.
• The pull-up network (PUN), built with P-MOSFETs, implements the dual of the PDN's logic. If the N-MOSFETs are in series, the corresponding P-MOSFETs will be in parallel.

This structure guarantees that for any valid input combination, either the PUN or the PDN is conducting, but never both at the same time.

CMOS NAND Gate

A 2-input NAND gate produces a LOW output only when both input A AND input B are HIGH.

1. Pull-Down Network (NMOS): To implement the A AND B logic, we connect two N-MOSFETs in series. The path to ground is only complete if both transistors are ON.
2. Pull-Up Network (PMOS): The dual of series is parallel. We connect two P-MOSFETs in parallel. If either A or B is LOW, at least one of the P-MOSFETs will turn ON, creating a path to $V_{DD}$.

The resulting circuit is shown below.

Let's trace its operation using the image above:

• (b) A=0, B=0: Q1 and Q2 are ON, connecting the output to $V_{DD}$. Q3 and Q4 are OFF. Output is HIGH.
• (c) A=0, B=1: Q1 is ON, connecting the output to $V_{DD}$. Q3 is OFF, breaking the path to ground. Output is HIGH.
• (Not shown, but symmetrical to c) A=1, B=0: Q2 is ON, connecting the output to $V_{DD}$. Q4 is OFF, breaking the path to ground. Output is HIGH.
• (d) A=1, B=1: Q1 and Q2 are OFF. Q3 and Q4 are ON, connecting the output to ground. Output is LOW.

This behavior perfectly matches the truth table for a NAND gate. The following video provides a dynamic visualization of this process.

CMOS NOR Gate

A 2-input NOR gate produces a LOW output if input A OR input B is HIGH.

1. Pull-Down Network (NMOS): To implement the A OR B logic, we connect two N-MOSFETs in parallel. The path to ground is complete if either transistor is ON.
2. Pull-Up Network (PMOS): The dual of parallel is series. We connect two P-MOSFETs in series. The path to $V_{DD}$ is only complete if both transistors are ON (i.e., when both A and B are LOW).

Let's trace the operation of the NOR gate on the right:

• A=0, B=0: Both P-MOSFETs are ON, completing the series path to $V_{DD}$. Both N-MOSFETs are OFF. Output is HIGH.
• A=0, B=1: The top P-MOSFET is ON, but the bottom one is OFF, breaking the series path to $V_{DD}$. The N-MOSFET for input B is ON, creating a parallel path to ground. Output is LOW.
• A=1, B=0: The bottom P-MOSFET is ON, but the top one is OFF, breaking the path. The N-MOSFET for input A is ON, creating a path to ground. Output is LOW.
• A=1, B=1: Both P-MOSFETs are OFF. Both N-MOSFETs are ON, creating two paths to ground. Output is LOW.

Once again, the behavior perfectly matches the NOR truth table. The video below provides the corresponding animation.

Conclusion

In this lesson, you have successfully bridged the gap between individual transistors and functional logic gates. By understanding the complementary "push-pull" design of CMOS, you can now see how all digital logic is built from these simple, repeating patterns.

Here are the key takeaways:

• CMOS logic uses complementary pairs of P-MOSFETs (in a pull-up network) and N-MOSFETs (in a pull-down network).
• This design results in nearly zero static power consumption because there is no direct path between the power supply and ground in a steady state.
• The pull-up and pull-down networks are duals of each other: a series arrangement in one corresponds to a parallel arrangement in the other.
• A NAND gate is built with N-MOSFETs in series and P-MOSFETs in parallel.
• A NOR gate is built with N-MOSFETs in parallel and P-MOSFETs in series.

You now have a foundational understanding of how the most common logic gates are physically realized. In our next lesson, we will zoom out slightly to compare the practical performance characteristics of the CMOS logic family you just learned about with TTL, an older technology. This will help you understand the real-world engineering trade-offs that led to CMOS dominating the world of digital electronics.