Identifying MOSFET Operating Regions from Terminal Voltages

Welcome back. In the previous lesson, you established the voltage convention $V_{XY}=V_X-V_Y$, and learned why $V_{GS}$ and $V_{DS}$ are the key NMOS variables, while $V_{SG}$ and $V_{SD}$ are often clearer for PMOS. We now use those voltages to make the first essential MOSFET decision: is the transistor off, operating as a voltage-controlled resistor, or operating as an approximate current source?

By the end of this lesson, you will be able to determine cutoff, triode (also called linear or ohmic), and saturation from terminal voltages for both NMOS and PMOS transistors. This classification must be done before choosing a drain-current equation, checking amplifier voltage swing, or interpreting a Cadence operating point.

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The physical idea: form a channel first

Consider an NMOS with its source at a lower potential than its drain. A sufficiently positive gate-to-source voltage attracts electrons beneath the oxide and creates an n-type inversion layer connecting source and drain. The minimum voltage needed to form a useful channel is the threshold voltage $V_{TN}$.

For a first-pass long-channel model:

• If $V_{GS}$ is below threshold, there is no strong inversion channel.
• If $V_{GS}$ exceeds threshold, a channel exists.
• Once a channel exists, $V_{DS}$ decides whether the channel reaches all the way to the drain or pinches off near the drain.

The quantity that measures how strongly the channel has been created is the overdrive voltage:

$$V_{OV}=V_{GS}-V_{TN}$$

For an NMOS to be on in the usual strong-inversion model, $V_{OV}$ must be positive.

Do not confuse threshold voltage with a fixed universal value such as $0.7\mathrm{V}$. It depends on process, device dimensions, temperature, and body bias. In a circuit problem, use the value given. Later, you will see how a source-to-body voltage changes the effective threshold through body effect.

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NMOS: channel continuity decides triode versus saturation

For an NMOS, the gate voltage relative to the source is $V_{GS}$. At the drain end of the channel, however, the relevant quantity is gate voltage relative to the drain:

$$V_{GD}=V_G-V_D$$

Using the source-referenced variables from the previous lesson:

$$V_{GD}=V_{GS}-V_{DS}$$

This identity gives a direct physical test.

If the gate-to-drain voltage remains above threshold,

$$V_{GD}>V_{TN}$$

then inversion exists even at the drain end. The channel is continuous from source to drain, and the NMOS is in triode.

If increasing $V_{DS}$ makes the gate-to-drain voltage fall to threshold,

$$V_{GD}=V_{TN}$$

the channel just reaches pinch-off at the drain end. Substituting $V_{GD}=V_{GS}-V_{DS}$ gives:

$$V_{DS}=V_{GS}-V_{TN}=V_{OV}$$

This is the boundary between triode and saturation.

If $V_{DS}$ rises beyond this value, the channel is pinched off near the drain and the NMOS is in saturation:

$$V_{DS}\ge V_{OV}$$

Pinch-off does not mean that drain current stops. Electrons still travel from the source through the channel and are swept through the high-field depletion region to the drain. Instead, in the ideal long-channel model, increasing $V_{DS}$ further has little effect on current. That approximate current-source behavior is why analog amplifiers usually bias their transistors in saturation.

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The NMOS decision table

Assume the intended NMOS orientation: source is the lower-potential terminal, drain is at the same or a higher potential, and the body junctions remain reverse biased.

Region	Voltage conditions	Physical interpretation
Cutoff	$V_{GS}\le V_{TN}$	No strong-inversion channel; $I_D$ is approximated as zero.
Triode / linear / ohmic	$V_{GS}>V_{TN}$ and $0\le V_{DS}<V_{OV}$	A continuous channel joins source and drain; the device behaves approximately as a gate-controlled resistance.
Saturation	$V_{GS}>V_{TN}$ and $V_{DS}\ge V_{OV}$	The channel pinches off at the drain end; the device behaves approximately as a gate-controlled current source.

The same triode-versus-saturation test can be stated with $V_{GD}$:

$$\text{Triode: }{V}_{GD}>V_{TN}$$ $$\text{Saturation: }{V}_{GD}\le V_{TN}$$

This version is especially useful when the gate and drain voltages are immediately visible in a schematic.

The equality case

At the exact condition

$$V_{DS}=V_{OV}$$

the device is at the boundary between triode and saturation. In hand analysis, it is usually acceptable to call this the saturation boundary. In a simulator, the displayed region label can depend on the compact model and its internal tolerances. The important fact is that there is zero saturation margin: a small output-voltage change can move the transistor into triode.

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PMOS: use positive source-referenced quantities

For a PMOS in normal operation, the source is at the higher voltage. The PMOS threshold is negative:

$$V_{TP}<0$$

You could use $V_{GS}$ and $V_{DS}$, which will normally be negative. For practical hand analysis, it is much cleaner to use positive PMOS voltage magnitudes:

$$V_{SG}=V_S-V_G$$ $$V_{SD}=V_S-V_D$$

Define a positive PMOS overdrive:

$$V_{OV,p}=V_{SG}-|V_{TP}|$$

The PMOS region tests have exactly the same structure as the NMOS tests:

Region	PMOS condition
Cutoff	$V_{SG}\le |V_{TP}|$
Triode	$V_{SG}>|V_{TP}|$ and $0\le V_{SD}<V_{OV,p}$
Saturation	$V_{SG}>|V_{TP}|$ and $V_{SD}\ge V_{OV,p}$

For PMOS, saturation can also be recognized from the gate-to-drain voltage. A PMOS is saturated when the gate is not sufficiently below the drain to sustain inversion at the drain end.

The symmetry is worth remembering:

• NMOS: compare $V_{DS}$ with $V_{GS}-V_{TN}$.
• PMOS: compare $V_{SD}$ with $V_{SG}-|V_{TP}|$.

The sign conventions differ, but the physical story is the same: gate voltage establishes the channel; drain-to-source voltage determines whether the channel remains continuous at the drain end.

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Worked classifications from terminal voltages

Example 1: NMOS in cutoff

Suppose:

$$V_G=0.40\mathrm{V}$$ $$V_S=0.10\mathrm{V}$$ $$V_D=1.20\mathrm{V}$$ $$V_{TN}=0.50\mathrm{V}$$

First calculate the controlling gate-source voltage:

$$V_{GS}=V_G-V_S=0.40-0.10=0.30\mathrm{V}$$

Since

$$V_{GS}<V_{TN}$$

the transistor is in cutoff.

Notice that $V_D$ is high, so $V_{DS}$ is high as well. That does not turn the device on. A drain voltage cannot create the inversion channel that the gate has failed to create.

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Example 2: NMOS in triode

Now let:

$$V_G=0.95\mathrm{V}$$ $$V_S=0.10\mathrm{V}$$ $$V_D=0.30\mathrm{V}$$ $$V_{TN}=0.50\mathrm{V}$$

Calculate the gate-source voltage and overdrive:

$$V_{GS}=0.95-0.10=0.85\mathrm{V}$$ $$V_{OV}=V_{GS}-V_{TN}=0.85-0.50=0.35\mathrm{V}$$

Then calculate the drain-source voltage:

$$V_{DS}=0.30-0.10=0.20\mathrm{V}$$

The device is on because $V_{GS}>V_{TN}$, and:

$$V_{DS}<V_{OV}$$

Therefore, the NMOS is in triode.

You can confirm this with the gate-to-drain form:

$$V_{GD}=V_G-V_D=0.95-0.30=0.65\mathrm{V}$$

Since

$$V_{GD}>V_{TN}$$

the channel persists at the drain end, which is exactly the triode condition.

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Example 3: NMOS in saturation

Keep the same gate and source voltages, but raise the drain voltage:

$$V_G=0.95\mathrm{V}$$ $$V_S=0.10\mathrm{V}$$ $$V_D=0.80\mathrm{V}$$ $$V_{TN}=0.50\mathrm{V}$$

The overdrive remains:

$$V_{OV}=0.35\mathrm{V}$$

But now:

$$V_{DS}=0.80-0.10=0.70\mathrm{V}$$

Since

$$V_{DS}>V_{OV}$$

the NMOS is in saturation.

Equivalently:

$$V_{GD}=0.95-0.80=0.15\mathrm{V}$$

Since

$$V_{GD}<V_{TN}$$

the drain end cannot remain inverted. The channel pinches off near the drain.

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Example 4: PMOS classification

Consider a PMOS with:

$$V_S=1.80\mathrm{V}$$ $$V_G=1.10\mathrm{V}$$ $$V_D=1.50\mathrm{V}$$ $$V_{TP}=-0.45\mathrm{V}$$

Use positive PMOS source-referenced quantities:

$$V_{SG}=1.80-1.10=0.70\mathrm{V}$$ $$V_{OV,p}=V_{SG}-|V_{TP}|=0.70-0.45=0.25\mathrm{V}$$ $$V_{SD}=1.80-1.50=0.30\mathrm{V}$$

The PMOS is on because:

$$V_{SG}>|V_{TP}|$$

And since:

$$V_{SD}>V_{OV,p}$$

it is in saturation.

If the drain instead rose to $1.65\mathrm{V}$, then:

$$V_{SD}=1.80-1.65=0.15\mathrm{V}$$

Because $V_{SD}<V_{OV,p}$, the same PMOS would be in triode.

This is an important amplifier-design point: for a PMOS current-source load near $V_{DD}$, allowing its drain voltage to rise too close to its source can push it out of saturation.

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A reliable classification workflow

For every MOSFET in a DC circuit, use the same sequence.

1. Identify the device type and intended source.
   For a normally connected NMOS, the source is the lower-voltage terminal. For a normally connected PMOS, it is the higher-voltage terminal.

2. Calculate source-referenced terminal voltages.
   Use $V_{GS}$ and $V_{DS}$ for NMOS; use $V_{SG}$ and $V_{SD}$ for PMOS.

3. Check whether the transistor is on.
   Compare $V_{GS}$ with $V_{TN}$, or $V_{SG}$ with $|V_{TP}|$.

4. Calculate overdrive only if the transistor is on.

5. Compare drain-source voltage with overdrive.
   A smaller drain-source voltage gives triode operation; a sufficiently large drain-source voltage gives saturation.

6. Check the physical assumptions.
   The usual three-region rules assume the body-source and body-drain junctions are not forward biased and that source and drain have their intended roles.

If circuit node voltages are not known initially because they depend on $I_D$, the procedure is slightly different: assume a region, solve the circuit using that region’s current equation, then verify the region inequalities. The next lesson will develop the drain-current equations needed for that process.

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Two practical cautions

Saturation is not the same as “fully on”

In digital-switch language, a low-resistance MOSFET is often described as “on.” For analog design, that wording can be misleading:

• Triode means the MOSFET is acting relatively resistive.
• Saturation means the MOSFET is acting more like a controlled current source.

Most common-source amplifiers, differential pairs, current mirrors, and cascode stages require selected transistors to remain in saturation over their intended signal swing.

Saturation current is not perfectly constant

The ideal long-channel model says that saturation current is independent of $V_{DS}$. Real MOSFETs exhibit channel-length modulation: as $V_{DS}$ increases, the pinch-off region extends and the effective channel becomes slightly shorter. The drain current then increases somewhat with $V_{DS}$.

Channel-length modulation is not a separate basic operating region. The device is still in saturation when:

$$V_{DS}\ge V_{OV}$$

Later, this non-ideal slope will become the finite output resistance $r_o$, which limits amplifier gain.

For a brief Cadence-oriented observation, set an NMOS gate voltage to a value above threshold, keep the source and body at ground, and run a DC sweep of $V_D$. The transition near

$$V_{DS}\approx V_{OV}$$

is the triode-to-saturation boundary. Past that point, a real-device $I_D$ curve will usually retain a small upward slope rather than becoming perfectly flat.

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Key takeaways

A MOSFET operating region is determined by its terminal voltages and threshold voltage.

For an NMOS:

$$V_{OV}=V_{GS}-V_{TN}$$ $$V_{GS}\le V_{TN}⟹\text{cutoff}$$ $$V_{GS}>V_{TN}\text{ and }{V}_{DS}<V_{OV}⟹\text{triode}$$ $$V_{GS}>V_{TN}\text{ and }{V}_{DS}\ge V_{OV}⟹\text{saturation}$$

For a PMOS, use $V_{SG}$, $V_{SD}$, and the positive threshold magnitude $|V_{TP}|$. The structure of the test is identical.

The most useful physical interpretation is this: triode means the inversion channel reaches from source to drain; saturation means the channel pinches off at the drain end but current continues to flow. In the next lesson, you will turn these region conditions into quantitative long-channel NMOS and PMOS drain-current equations, including channel-length modulation.