Calculating Long-Channel MOSFET Drain Current with Channel-Length Modulation

Welcome back. Previously, you learned to classify a MOSFET as cutoff, triode, or saturation from its terminal voltages. That classification now becomes quantitative: each region has a drain-current equation. These equations are the starting point for finding DC bias points, choosing transistor dimensions, and eventually designing amplifier stages.

In this lesson, you will calculate long-channel NMOS and PMOS drain current from $W$, $L$, terminal voltages, and process parameters. You will also include channel-length modulation, the real-device effect that prevents a saturated MOSFET from being a perfectly constant current source.

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From a formed channel to a current equation

The long-channel MOSFET model assumes strong inversion, a sufficiently long channel, and no body effect unless an effective threshold voltage is already supplied. For now, treat $V_{TN}$ or $V_{TP}$ as known constants.

For an NMOS, define the overdrive voltage:

$$V_{OV}=V_{GS}-V_{TN}$$

A positive $V_{OV}$ means that an inversion channel exists. Along that channel, however, voltage rises from the source toward the drain. Therefore, the gate-to-channel voltage is strongest at the source and weakest near the drain. The channel becomes progressively thinner as $V_{DS}$ increases.

The gradual-channel model represents this by integrating the channel conductance from source to drain. The result is the familiar triode-region equation. You do not need to reproduce its full derivation from memory for most circuit problems, but you should understand why the result contains both a term proportional to $V_{DS}$ and a term proportional to $V_{DS}^2$.

Two process-and-geometry quantities appear repeatedly:

$$k_n^{\prime }={\mu }_n{C}_{ox}$$ $${\beta }_n=k_n^{\prime }\frac{W}{L}$$

where:

• ${\mu }_n$ is electron mobility.
• $C_{ox}$ is gate-oxide capacitance per unit area.
• $k_n^{\prime }$ is the NMOS process transconductance parameter, usually expressed in $A/{\mathrm{V}}^2$.
• $W$ is channel width and $L$ is channel length.
• ${\beta }_n$ is the device transconductance parameter.

Because $W/L$ is dimensionless, you may use micrometres for both $W$ and $L$, provided they use the same unit.

A wider transistor has more parallel current paths and carries more current. A longer transistor has a more resistive channel and carries less current. Thus, for unchanged terminal voltages,

$$I_D\propto \frac{W}{L}$$

Different textbooks use slightly different notation. Some call $k_n^{\prime }W/L$ simply $k_n$, while others use $K_n$. Before substituting numbers, always establish whether the stated parameter already includes $W/L$.

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The long-channel NMOS current equations

Using the conventional NMOS drain current $I_D$, positive from drain to source, the three-region model is as follows.

Region	Conditions	Long-channel current
Cutoff	$V_{GS}\le V_{TN}$	$I_D\simeq 0$
Triode	$V_{GS}>V_{TN}$, $0\le V_{DS}<V_{OV}$	$I_D={\beta }_n\left(V_{OV}{V}_{DS}-\frac{V_{DS}^2}{2}\right)$
Saturation, ideal	$V_{GS}>V_{TN}$, $V_{DS}\ge V_{OV}$	$I_D=\frac{1}{2}{\beta }_n{V}_{OV}^2$

The triode expression can also be written directly in terms of $V_{GS}$:

$$I_D=k_n^{\prime }\frac{W}{L}\left[(V_{GS}-V_{TN})V_{DS}-\frac{V_{DS}^2}{2}\right]$$

The ideal saturation equation is:

$$I_D=\frac{1}{2}{k}_n^{\prime }\frac{W}{L}(V_{GS}-V_{TN}{)}^2$$

At the boundary $V_{DS}=V_{OV}$, both equations give the same result:

$$I_D=\frac{1}{2}{\beta }_n{V}_{OV}^2$$

This agreement is useful for checking that the equations are physically consistent.

The low-$V_{DS}$ limit

When $V_{DS}$ is much smaller than $V_{OV}$, the quadratic term is relatively small:

$$\frac{V_{DS}^2}{2}\ll V_{OV}{V}_{DS}$$

Then:

$$I_D\approx {\beta }_n{V}_{OV}{V}_{DS}$$

This has the form of Ohm’s law, so the MOSFET behaves approximately as a resistor:

$$R_{DS}\approx \frac{1}{{\beta }_n{V}_{OV}}$$

This approximation is useful for MOS switches, but analog amplifiers normally aim to keep their signal transistors in saturation instead.

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PMOS equations: use positive voltage and current magnitudes

A PMOS has a negative threshold voltage:

$$V_{TP}<0$$

Although you can write PMOS equations using negative $V_{GS}$, $V_{DS}$, and $I_D$, that approach often creates avoidable sign errors. For hand analysis, use the positive source-referenced quantities:

$$V_{SG}=V_S-V_G$$ $$V_{SD}=V_S-V_D$$ $$V_{OV,p}=V_{SG}-|V_{TP}|$$

Define $I_{SD}$ as the positive current magnitude flowing from source to drain. Then the PMOS equations have exactly the same form as the NMOS equations:

Region	Conditions	PMOS current magnitude
Cutoff	$V_{SG}\le |V_{TP}|$	$I_{SD}\simeq 0$
Triode	$V_{SG}>|V_{TP}|$, $0\le V_{SD}<V_{OV,p}$	$I_{SD}={\beta }_p\left(V_{OV,p}{V}_{SD}-\frac{V_{SD}^2}{2}\right)$
Saturation, ideal	$V_{SG}>|V_{TP}|$, $V_{SD}\ge V_{OV,p}$	$I_{SD}=\frac{1}{2}{\beta }_p{V}_{OV,p}^2$

where:

$${\beta }_p=k_p^{\prime }\frac{W}{L}$$ $$k_p^{\prime }={\mu }_p{C}_{ox}$$

For a PMOS, ${\mu }_p$ is lower than ${\mu }_n$, so $k_p^{\prime }$ is usually smaller than $k_n^{\prime }$. In practical CMOS design, a PMOS is often made wider than an NMOS to obtain comparable current drive.

If a problem explicitly requests the conventional terminal current $I_D$, defined as positive entering the drain, then normal PMOS operation gives:

$$I_D=-I_{SD}$$

State your convention clearly. In analog design calculations, reporting the positive magnitude $I_{SD}$ is usually clearest.

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Channel-length modulation: saturation current is not perfectly constant

The ideal saturation equation predicts a flat $I_D$-versus-$V_{DS}$ curve. A real MOSFET does not behave that way.

After pinch-off, increasing $V_{DS}$ expands the drain depletion region. This moves the pinch-off point slightly toward the source and reduces the effective channel length. Since drain current is inversely related to channel length, the drain current rises with $V_{DS}$.

The standard first-order hand-calculation model modifies the saturation equation:

$$I_D=\frac{1}{2}{\beta }_n{V}_{OV}^2(1+{\lambda }_n{V}_{DS})$$

Here, ${\lambda }_n$ is the channel-length modulation parameter, with units of ${\mathrm{V}}^{-1}$.

For PMOS, using positive magnitudes:

$$I_{SD}=\frac{1}{2}{\beta }_p{V}_{OV,p}^2(1+{\lambda }_p{V}_{SD})$$

The parameter $\lambda$ is generally larger for shorter channel lengths. Therefore, short-channel devices exhibit a stronger dependence of saturation current on output voltage. This is one reason that increasing $L$ can improve analog gain, although it also costs area and capacitance.

The modulation equation belongs to saturation analysis. Do not automatically attach the factor $(1+\lambda V_{DS})$ to the basic long-channel triode equation unless a particular model or problem explicitly instructs you to do so.

A convenient way to separate the ideal current from the modulation correction is:

$$I_{D0}=\frac{1}{2}{\beta }_n{V}_{OV}^2$$ $$I_D=I_{D0}(1+{\lambda }_n{V}_{DS})$$

Thus, if two saturated operating points have the same $V_{GS}$ but different $V_{DS}$, their current ratio is:

$$\frac{I_{D2}}{I_{D1}}=\frac{1+{\lambda }_n{V}_{DS2}}{1+{\lambda }_n{V}_{DS1}}$$

Later, the same effect will produce the finite small-signal output resistance $r_o$, which strongly limits the gain of a common-source amplifier.

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A reliable current-calculation workflow

For every transistor, use the following sequence:

1. Calculate the source-referenced voltages.
   NMOS uses $V_{GS}$ and $V_{DS}$. PMOS uses $V_{SG}$ and $V_{SD}$.

2. Check whether the device is on.
   Compare $V_{GS}$ with $V_{TN}$ for NMOS, or $V_{SG}$ with $|V_{TP}|$ for PMOS.

3. Calculate overdrive.
   Use $V_{OV}=V_{GS}-V_{TN}$ for NMOS and $V_{OV,p}=V_{SG}-|V_{TP}|$ for PMOS.

4. Determine the operating region.
   Compare the applicable drain-to-source voltage with overdrive.

5. Form $\beta$.
   Multiply the process parameter by $W/L$.

6. Use the equation for the verified region.
   In saturation, include channel-length modulation if $\lambda$ is given or requested.

7. Check units and physical plausibility.
   With $k^{\prime }$ in $A/{\mathrm{V}}^2$, current must come out in amperes.

When circuit voltages depend on the unknown drain current, assume a plausible region, solve using its equation, then verify the region conditions using the resulting node voltages. The next module will use this exact approach for complete biased amplifier stages.

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Worked examples

NMOS in triode

Given:

$$k_n^{\prime }=200\mu A/{\mathrm{V}}^2$$ $$\frac{W}{L}=10$$ $$V_{GS}=0.90\mathrm{V}$$ $$V_{TN}=0.45\mathrm{V}$$ $$V_{DS}=0.20\mathrm{V}$$

First calculate the overdrive and device parameter:

$$V_{OV}=0.90-0.45=0.45\mathrm{V}$$ $${\beta }_n=200\mu A/{\mathrm{V}}^2\times 10=2mA/{\mathrm{V}}^2$$

Since:

$$V_{DS}=0.20\mathrm{V}<V_{OV}=0.45\mathrm{V}$$

the transistor is in triode. Therefore:

$$I_D={\beta }_n\left(V_{OV}{V}_{DS}-\frac{V_{DS}^2}{2}\right)$$ $$I_D=2mA/{\mathrm{V}}^2\left[(0.45)(0.20)-\frac{(0.20{)}^2}{2}\right]$$ $$I_D=140\mu \mathrm{A}$$

The result is below the ideal saturation current for the same $V_{GS}$, as expected, because $V_{DS}$ has not yet reached the saturation boundary.

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NMOS in saturation with channel-length modulation

Given:

$$k_n^{\prime }=200\mu A/{\mathrm{V}}^2$$ $$\frac{W}{L}=10$$ $$V_{GS}=0.70\mathrm{V}$$ $$V_{TN}=0.45\mathrm{V}$$ $$V_{DS}=1.20\mathrm{V}$$ $${\lambda }_n=0.08{\mathrm{V}}^{-1}$$

The overdrive and device parameter are:

$$V_{OV}=0.70-0.45=0.25\mathrm{V}$$ $${\beta }_n=2mA/{\mathrm{V}}^2$$

The region check is:

$$V_{DS}=1.20\mathrm{V}>V_{OV}=0.25\mathrm{V}$$

Thus the device is saturated. The ideal saturation current is:

$$I_{D0}=\frac{1}{2}(2mA/{\mathrm{V}}^2)(0.25\mathrm{V}{)}^2$$ $$I_{D0}=62.5\mu \mathrm{A}$$

Now apply channel-length modulation:

$$I_D=62.5\mu \mathrm{A}\left[1+(0.08{\mathrm{V}}^{-1})(1.20\mathrm{V})\right]$$ $$I_D=68.5\mu \mathrm{A}$$

Channel-length modulation increases the current by about $6\mu \mathrm{A}$, or $9.6\%$, relative to the ideal model.

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PMOS in saturation with channel-length modulation

Given:

$$k_p^{\prime }=80\mu A/{\mathrm{V}}^2$$ $$\frac{W}{L}=20$$ $$V_S=1.80\mathrm{V}$$ $$V_G=1.15\mathrm{V}$$ $$V_D=0.90\mathrm{V}$$ $$V_{TP}=-0.40\mathrm{V}$$ $${\lambda }_p=0.10{\mathrm{V}}^{-1}$$

Use the positive PMOS variables:

$$V_{SG}=1.80-1.15=0.65\mathrm{V}$$ $$V_{SD}=1.80-0.90=0.90\mathrm{V}$$ $$V_{OV,p}=0.65-0.40=0.25\mathrm{V}$$ $${\beta }_p=80\mu A/{\mathrm{V}}^2\times 20=1.6mA/{\mathrm{V}}^2$$

Because:

$$V_{SD}=0.90\mathrm{V}>V_{OV,p}=0.25\mathrm{V}$$

the PMOS is in saturation. Its current magnitude is:

$$I_{SD}=\frac{1}{2}(1.6mA/{\mathrm{V}}^2)(0.25\mathrm{V}{)}^2\left[1+(0.10{\mathrm{V}}^{-1})(0.90\mathrm{V})\right]$$ $$I_{SD}=54.5\mu \mathrm{A}$$

Thus the conventional PMOS drain current, if defined as positive entering the drain, is:

$$I_D=-54.5\mu \mathrm{A}$$

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A short Cadence observation

In Cadence, build a simple NMOS testbench with source and bulk connected to ground. Set $V_G$ to a constant value above threshold, then perform a DC sweep of the drain voltage from $0\mathrm{V}$ to $V_{DD}$.

Use a sufficiently wide device and inspect the plot of $I_D$ versus $V_{DS}$:

• At low $V_{DS}$, the curve should rise strongly and nonlinearly: triode operation.
• Near $V_{DS}\approx V_{OV}$, the curve bends toward saturation.
• Beyond that point, a real PDK model will show a nonzero slope due to channel-length modulation and other short-channel effects.

Repeat the sweep with a longer $L$. The long-channel equations predict a smaller $\lambda$, and the saturated curves should generally become flatter. Exact numerical agreement is not expected: Cadence compact models include effects beyond this first-order long-channel model.

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Key takeaways

The long-channel drain-current equations connect transistor dimensions and terminal voltages to DC current.

For NMOS:

$${\beta }_n=k_n^{\prime }\frac{W}{L}$$ $$I_D={\beta }_n\left(V_{OV}{V}_{DS}-\frac{V_{DS}^2}{2}\right)$$

in triode, and:

$$I_D=\frac{1}{2}{\beta }_n{V}_{OV}^2(1+{\lambda }_n{V}_{DS})$$

in saturation when channel-length modulation is included.

For PMOS, use positive quantities $V_{SG}$, $V_{SD}$, $V_{OV,p}$, and $I_{SD}$. The equations have the same form, with PMOS parameters.

The most important habit is to determine the operating region before using an equation, and to verify that region after solving a circuit. Next, you will use these equations inside complete biased MOS stages to calculate DC operating points, voltage headroom, and saturation margins.