Analog Integrated Circuit Design

Apply Kirchhoff’s current law to solve single-node and two-node resistive circuits.

Apply Kirchhoff’s voltage law to solve series and multi-loop resistive circuits.

Represent a capacitor by its complex impedance and calculate the response of a first-order RC circuit.

Convert voltage and power ratios between linear units and decibels.

Calculate long-channel MOSFET drain current in each operating region, including channel-length modulation.

Calculate the DC operating point and voltage headroom of a biased MOSFET stage.

Calculate MOSFET transconductance, output resistance, and body transconductance at a specified bias point.

Construct the low-frequency small-signal equivalent circuit of a MOSFET, including body effect and channel-length modulation.

Derive the midband gain and terminal resistances of a common-source amplifier.

Derive the midband gain and terminal resistances of a common-gate amplifier.

Derive the midband gain and terminal resistances of a source follower.

Select bias current and device overdrive to meet a single-stage gain, power, and output-swing target.

Use Cadence operating-point and AC analyses to verify the bias point, gain, and terminal resistances of a MOS amplifier.

Decompose two input signals into differential-mode and common-mode components.

Calculate current steering in a matched MOS differential pair for small and large differential inputs.

Derive the differential-mode gain of a resistively loaded MOS differential pair using half-circuit analysis.

Calculate the input common-mode range and output-voltage range of a differential pair.

Analyze a current-mirror active load as a differential-to-single-ended converter.

Calculate differential gain, common-mode gain, and common-mode rejection ratio for an actively loaded differential stage.

Choose tail current and transistor overdrives to meet gain, slew-rate, input-range, swing, and power targets.

Verify differential transfer, common-mode range, gain, and slew rate using Cadence DC, AC, and transient analyses.

Design a basic MOS current mirror for a specified reference current and current-scaling ratio.

Calculate the compliance voltage and finite-output-resistance error of a MOS current source or sink.

Analyze a cascode current mirror and quantify its output-resistance improvement and headroom cost.

Design a high-swing cascode current sink for specified output resistance and minimum output voltage.

Analyze a MOS Wilson current source and quantify its accuracy and output resistance.

Design a MOS Widlar-type current source for a small output current using source degeneration.

Configure a current mirror as a current amplifier with a specified current gain.

Design a self-biased current network with a startup circuit that avoids the zero-current state.

Derive the gain and output resistance of a single-ended cascode amplifier.

Calculate the input and output voltage limits of a telescopic cascode stage.

Analyze the signal-current paths and bias requirements of a folded-cascode stage.

Derive the gain and output resistance of an actively loaded differential telescopic cascode amplifier.

Derive the gain and output resistance of an actively loaded differential folded-cascode amplifier.

Compare telescopic and folded cascodes in gain, bandwidth, input range, output swing, noise, and power.

Size a cascode stage to meet specified gain, bandwidth, input-range, output-swing, and power constraints.

Verify cascode biasing, gain, bandwidth, and voltage ranges in Cadence.

Construct a high-frequency MOSFET small-signal model using intrinsic and junction capacitances.

Apply Miller’s theorem to calculate equivalent input and output capacitances around an inverting gain stage.

Associate circuit nodes with poles by estimating node resistance and capacitance.

Derive the dominant poles and bandwidth of a common-source amplifier.

Derive the dominant poles and bandwidth of common-gate and source-follower amplifiers.

Analyze the pole structure and frequency response of a differential pair.

Explain how cascoding changes the Miller effect, pole locations, and bandwidth.

Extract poles, gain-bandwidth product, and unity-gain frequency from Cadence AC simulations.

Calculate mean, variance, power spectral density, and RMS value for a stationary noise signal.

Calculate the integrated thermal-noise voltage or current of a resistor over a specified bandwidth.

Calculate MOSFET channel thermal-noise and flicker-noise contributions.

Refer circuit noise to an amplifier’s input or output using its transfer gain.

Derive the output and input-referred noise of a common-source amplifier.

Compare the principal noise contributions of common-gate and source-follower stages.

Calculate the input-referred noise of a MOS differential amplifier.

Use Cadence noise analysis to identify dominant contributors and evaluate integrated input-referred noise.

Derive closed-loop gain from forward gain and feedback factor for a negative-feedback system.

Calculate gain desensitivity and bandwidth change from loop gain.

Classify feedback amplifiers as series-shunt, shunt-shunt, series-series, or shunt-series.

Determine how each feedback topology changes input and output resistance.

Include source, load, and feedback-network loading when calculating loop gain and closed-loop gain.

Use return-ratio analysis to find loop gain without assuming unilateral amplifier blocks.

Calculate feedback’s effect on distortion and internally generated noise.

Construct a Cadence loop-gain testbench that preserves the circuit’s DC bias conditions.

Define and measure DC gain, unity-gain frequency, input offset, ICMR, CMRR, output swing, slew rate, PSRR, and power dissipation.

Design a one-stage telescopic or folded-cascode op-amp from a specified gain, bandwidth, range, swing, and power budget.

Derive the low-frequency gain and output swing of a two-stage op-amp with a common-source second stage.

Analyze a two-stage op-amp that uses a cascode second stage.

Calculate positive and negative slew rates from charging paths and available stage currents.

Identify transistor-level mechanisms that limit op-amp input common-mode range and output swing.

Calculate positive and negative power-supply rejection from small-signal supply paths.

Apply gain boosting to a cascode stage and calculate the resulting gain and headroom constraints.

Construct a loop-gain Bode plot from an op-amp’s poles and zeros.

Calculate gain margin and phase margin from loop-gain magnitude and phase.

Predict closed-loop ringing and settling behavior from phase margin.

Derive the uncompensated pole locations of a two-stage op-amp from its high-impedance nodes.

Derive pole splitting and the right-half-plane zero produced by Miller compensation.

Choose a compensation capacitor to meet unity-gain frequency, phase-margin, and slew-rate targets.

Use a nulling resistor to relocate or remove the Miller-compensation zero.

Compare Miller, cascode/Ahuja, feedforward, and nested-Miller compensation for two-stage and multistage amplifiers.

Calculate line sensitivity and output resistance for a practical current reference.

Explain how self-biased reference circuits become supply independent and why they require startup circuitry.

Generate a proportional-to-absolute-temperature current from a difference in device voltages.

Generate a complementary-to-absolute-temperature voltage or current from a junction-voltage characteristic.

Combine PTAT and CTAT quantities to obtain a first-order temperature-independent reference.

Calculate the nominal value and first-order temperature coefficient of a bandgap-style reference.

Design a constant-transconductance bias circuit using resistor and device-ratio constraints.

Evaluate reference accuracy across supply, temperature, process corners, and startup conditions in Cadence.

Translate an op-amp specification into an architecture choice and budgets for gain, current, headroom, and noise.

Calculate initial transistor dimensions, bias currents, and compensation components for the selected architecture.

Build DC testbenches for input common-mode range, output swing, power dissipation, CMRR, and PSRR.

Build an AC loop-gain testbench to measure DC gain, unity-gain frequency, phase margin, and gain margin.

Build transient testbenches to measure slew rate, settling time, and large-signal recovery.

Measure input-referred noise and identify the devices that dominate the noise budget.

Run process-voltage-temperature corners and Monte Carlo mismatch analyses on the completed design.

Iterate device sizes and bias conditions to resolve failed specifications and document the final design trade-offs.