NMOS and PMOS Terminal Labels, Voltages, and Current Directions

You have finished the passive-circuit foundation: KCL/KVL, equivalent circuits, RC transients, and sinusoidal frequency response. We now begin the MOSFET portion of the course, where a consistent labeling discipline becomes essential. Nearly every later result—operating regions, drain-current equations, small-signal models, gain, and voltage swing—depends on knowing exactly what a voltage such as $V_{GS}$ or a current such as $I_D$ means.

This lesson establishes that discipline. You will identify all four MOSFET terminals, write terminal voltages with an unambiguous sign convention, distinguish conventional current from electron motion, and handle NMOS and PMOS devices without silently changing definitions.

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A MOSFET is fundamentally a four-terminal device

An integrated-circuit MOSFET has four electrical terminals:

• Gate $G$: the control terminal.
• Drain $D$: one end of the channel.
• Source $S$: the other end of the channel.
• Body $B$, also called the bulk or substrate: the semiconductor region surrounding the device.

The name MOSFET stands for metal-oxide-semiconductor field-effect transistor. The gate is separated from the semiconductor by a very thin insulating oxide. Consequently, the gate controls the channel through an electric field rather than through a direct conducting connection.

At DC, the ideal MOS gate draws no current:

$$I_G\approx 0$$

That does not mean the gate is irrelevant. Its voltage relative to the source and body strongly controls the drain-source current.

In many circuit diagrams, the body connection is omitted. This is a shorthand, not a claim that the body has disappeared. The designer assumes it is connected properly in the fabrication technology.

For ordinary CMOS analog circuits:

Device	Channel	Typical body connection	Reason
NMOS	n-channel in p-type body	Lowest circuit potential, often ground	Keeps body junctions reverse biased
PMOS	p-channel in n-well body	Highest circuit potential, often $V_{DD}$	Keeps body junctions reverse biased

The body forms PN junctions with the source and drain. If those junctions become forward biased, they conduct like diodes, usually violating the intended MOSFET behavior. Therefore, body voltage is not just a drawing detail; it constrains usable signal voltages and later causes the body effect.

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Reading symbols and terminal order

The supplied reference image shows NMOS and PMOS symbols with all four terminals visible.

Do not identify source and drain merely from whether they are drawn above or below a symbol. Schematics may be rotated or mirrored. Instead, use the terminal labels, the symbol convention used by the design kit, and the applied voltages.

For a four-terminal MOSFET, the standard SPICE instance ordering is:

$$\boxed{\text{Mname drain gate source substrate model L=value W=value}}$$

For example, an NMOS with drain at out, gate at in, source and body at ground may appear conceptually as:

M1 out in 0 0 nmos_model L=0.5u W=10u

The first node after the name is always the drain, the second is the gate, the third is the source, and the fourth is the body. A swapped drain/source connection may simulate, but it changes the meanings of $V_{DS}$, $V_{GS}$, and the body-related voltages. It can also change behavior in a real IC because source and drain are not always perfectly interchangeable once body bias, layout, and process effects are included.

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The universal voltage convention

The safest convention is simple:

$$\boxed{V_{XY}=V_X-V_Y}$$

Read this as “the voltage at terminal $X$, measured with respect to terminal $Y$.” The subscript order tells you the subtraction order.

The important MOS terminal voltages are:

$$V_{GS}=V_G-V_S$$ $$V_{DS}=V_D-V_S$$ $$V_{BS}=V_B-V_S$$

You may also encounter:

$$V_{GD}=V_G-V_D$$ $$V_{DB}=V_D-V_B$$

These are not additional independent voltages. For example,

$$V_{GD}=V_G-V_D$$

can be rewritten as

$$V_{GD}=(V_G-V_S)-(V_D-V_S)$$

so that

$$\boxed{V_{GD}=V_{GS}-V_{DS}}$$

This identity is frequently useful in amplifier analysis.

A voltage label is not an assertion that the answer will be positive. It specifies a reference direction. For instance, if $V_G=0.3\mathrm{V}$ and $V_S=1.2\mathrm{V}$, then

$$V_{GS}=0.3-1.2=-0.9\mathrm{V}$$

A negative result is valid information: the gate lies below the source.

Why reference voltages to the source?

The channel is controlled primarily by gate voltage relative to the source, not by gate voltage relative to ground. This is why $V_{GS}$, rather than $V_G$, is central to MOSFET analysis.

Similarly, the drain-source voltage

$$V_{DS}=V_D-V_S$$

describes the voltage applied along the channel. In later lessons, $V_{GS}$ and $V_{DS}$ will tell us whether a MOSFET is in cutoff, triode, or saturation.

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NMOS voltage polarities

In its usual analog-amplifier connection, an NMOS has:

• source at a relatively low voltage,
• drain at a higher voltage,
• gate above the source when the device is on,
• body at the lowest available voltage.

Thus, typical NMOS signs are:

$$V_{GS}>0$$ $$V_{DS}>0$$

and, when body and source are tied together,

$$V_{BS}=0$$

Consider an NMOS with the following terminal voltages:

$$V_G=1.1\mathrm{V}$$ $$V_D=0.9\mathrm{V}$$ $$V_S=0.2\mathrm{V}$$ $$V_B=0\mathrm{V}$$

Then:

$$V_{GS}=1.1-0.2=0.9\mathrm{V}$$ $$V_{DS}=0.9-0.2=0.7\mathrm{V}$$ $$V_{BS}=0-0.2=-0.2\mathrm{V}$$

Notice that even though the body is at ground, $V_{BS}$ is negative because the source is above ground. Equivalently,

$$V_{SB}=V_S-V_B=+0.2\mathrm{V}$$

Later, positive $V_{SB}$ for an NMOS will be associated with body effect.

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PMOS voltage polarities

A PMOS is the complementary device. In its usual analog connection:

• source is at a relatively high voltage, often near $V_{DD}$,
• drain is lower than the source,
• gate must be below the source to turn the device on,
• body is connected to the highest supply voltage.

If we insist on using the same definitions,

$$V_{GS}=V_G-V_S$$

and

$$V_{DS}=V_D-V_S$$

then a normally conducting PMOS has:

$$V_{GS}<0$$ $$V_{DS}<0$$

This is completely correct. Negative values do not indicate an error.

For PMOS analysis, it is often more convenient to use source-referenced quantities with positive values:

$$\boxed{V_{SG}=V_S-V_G=-V_{GS}}$$ $$\boxed{V_{SD}=V_S-V_D=-V_{DS}}$$

In normal PMOS operation, these are positive:

$$V_{SG}>0$$ $$V_{SD}>0$$

Suppose a PMOS has:

$$V_S=1.8\mathrm{V}$$ $$V_G=1.0\mathrm{V}$$ $$V_D=0.7\mathrm{V}$$ $$V_B=1.8\mathrm{V}$$

Using the universal subtraction convention gives:

$$V_{GS}=1.0-1.8=-0.8\mathrm{V}$$ $$V_{DS}=0.7-1.8=-1.1\mathrm{V}$$

Using PMOS-friendly voltage variables gives:

$$V_{SG}=1.8-1.0=0.8\mathrm{V}$$ $$V_{SD}=1.8-0.7=1.1\mathrm{V}$$

Both descriptions state exactly the same physical voltages. Choose a convention deliberately and retain it throughout the calculation.

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Source and drain: physical symmetry versus circuit labels

A beginner-friendly rule is:

• For an NMOS, the source is normally the terminal at the lower voltage.
• For a PMOS, the source is normally the terminal at the higher voltage.

This rule fits the intended direction of carrier injection:

Device	Typical source voltage	Typical drain voltage	Carrier motion in channel
NMOS	Lower	Higher	Electrons move from source to drain
PMOS	Higher	Lower	Holes move from source to drain

At the physical level, source and drain diffusion regions are often made similarly, and a simple MOSFET can appear symmetric. But in analog circuit analysis, the designation matters because:

1. We define control voltage with respect to the source.
2. The body-source junction should remain reverse biased.
3. Body effect depends on the source-body voltage.
4. Real devices may have layout or process asymmetries.

The source is therefore not just “the lower pin on the drawing.” It is the terminal chosen to serve as the channel’s source under the intended bias condition.

The USC MOS theory notes summarize the practical rule well:

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Current directions: conventional current is the circuit convention

Circuit equations use conventional current, defined as the direction positive charge would move. Electron motion is opposite to conventional current.

NMOS

For an NMOS in normal operation:

• electrons move from source to drain;
• conventional drain current flows from drain to source.

Thus, we define positive drain current as entering the drain:

$$\boxed{I_D\text{ is positive when it enters the drain terminal}}$$

This is the current direction used by the usual NMOS drain-current equations.

PMOS

For a PMOS in normal operation:

• holes move from source to drain;
• conventional current also flows from source to drain.

Thus, physical conventional current enters the PMOS source and leaves its drain.

Here is where notation can become confusing. If you keep the universal terminal-current convention “current is positive when entering the named device terminal,” then normal PMOS drain current is negative:

$$i_D<0$$

because conventional current is leaving the drain rather than entering it.

For hand calculations, designers commonly avoid carrying this negative sign by defining a positive PMOS current magnitude:

$$\boxed{I_{SD}\text{ is positive from PMOS source to PMOS drain}}$$

or simply writing $I_D$ as a positive magnitude while explicitly stating that it refers to a PMOS current flowing from source to drain. Both practices occur in textbooks and design discussions.

The key is not which notation you choose. The key is never to mix them silently.

Quantity	NMOS in normal operation	PMOS in normal operation
Conventional channel current	Drain to source	Source to drain
Electron motion	Source to drain	Drain to source
Typical positive voltage notation	$V_{GS}$, $V_{DS}$	$V_{SG}$, $V_{SD}$
Common positive current magnitude	$I_D$, drain to source	$I_{SD}$, source to drain

A universal terminal-current check

When working rigorously, define every terminal current as positive into the transistor:

$$i_D+i_G+i_S+i_B=0$$

This is simply KCL applied to the device boundary.

At DC, gate current is ideally negligible:

$$i_G\approx 0$$

If the body current is also negligible, then:

$$i_D+i_S\approx 0$$

For a normally operating NMOS, $i_D>0$ and $i_S<0$. For a normally operating PMOS, $i_S>0$ and $i_D<0$. This single convention works for both device types and is especially useful in simulator outputs, where signs may otherwise be surprising.

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A reliable labeling workflow

Whenever you encounter a MOS transistor in a schematic, follow this sequence before writing an equation.

1. Identify device type.
   Determine whether it is NMOS or PMOS from the label, PDK symbol, or circuit context.

2. Label all terminals.
   Mark $G$, $D$, $S$, and $B$. If the body is omitted, state the assumed body connection.

3. Write the actual node voltages.
   Use values or names such as $V_{DD}$, ground, $V_{\mathrm{out}}$, and $V_{\mathrm{bias}}$.

4. Construct terminal-voltage differences from their definitions.
   For example,

   $$V_{GS}=V_G-V_S$$

   rather than relying on visual intuition.

5. State a current reference direction.
   For rigorous work, use positive current entering every named terminal. For PMOS magnitude calculations, clearly write whether current is $I_{SD}$ or a magnitude $|I_D|$.

6. Perform a physical reasonableness check.
   A normally on NMOS should generally have a positive $V_{GS}$; a normally on PMOS should generally have a positive $V_{SG}$.

This workflow prevents common errors before any algebra begins.

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Common mistakes to eliminate now

Treating $V_{GS}$ as “gate voltage”

$V_{GS}$ is not the gate voltage relative to ground. It is a difference:

$$V_{GS}=V_G-V_S$$

If the source moves, $V_{GS}$ changes even when the gate node remains fixed. This fact is the central idea behind the source follower studied later.

Changing the definition for PMOS without saying so

Do not write $V_{GS}=V_S-V_G$ merely because the device is PMOS. That quantity is named $V_{SG}$. Preserve the order in the subscript:

$$V_{GS}=V_G-V_S$$ $$V_{SG}=V_S-V_G$$

Assuming current direction from the arrow alone

MOS symbol-arrow conventions vary among drawing standards and PDKs. Use terminal labels and stated voltage/current references. In exam problems, the indicated current arrow or equation convention is authoritative.

Forgetting the body

Even when no body pin is visible, it is electrically present. An NMOS source raised above its grounded body, or a PMOS source pulled below its $V_{DD}$-connected body, can experience body effect. We will quantify this later.

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Key takeaways

A MOSFET is a four-terminal device with gate $G$, drain $D$, source $S$, and body $B$. In standard integrated CMOS use, the NMOS body is usually tied to the lowest supply and the PMOS body to the highest supply, preserving reverse-biased body junctions.

Use one universal voltage definition:

$$V_{XY}=V_X-V_Y$$

In particular:

$$V_{GS}=V_G-V_S$$ $$V_{DS}=V_D-V_S$$ $$V_{BS}=V_B-V_S$$

For NMOS devices, normal operation usually gives positive $V_{GS}$ and $V_{DS}$. For PMOS devices, the same universal definitions normally yield negative $V_{GS}$ and $V_{DS}$, so designers often use the positive quantities:

$$V_{SG}=-V_{GS}$$ $$V_{SD}=-V_{DS}$$

Conventional NMOS current normally flows drain to source, while conventional PMOS current normally flows source to drain. Electron motion is opposite to conventional current.

Next, you will use these terminal voltages to determine whether a MOSFET is in cutoff, triode, or saturation—the operating-region classification that determines which current model is valid.